Thin film transistors are field effect transistors (FETs) that offer major cost and density advantages. However, TFTs have some inferior characteristics such as lower gains and off-state leakage currents. Unlike the conventional FETs where the source, drain and channel regions are formed in the body of a single crystal substrate, the device regions of a TFT are formed in a polysilicon or an amorphous silicon layer (device layer) overlying a substrate. Since the polysilicon layer is formed at relatively lower temperatures and need not be within the body of the single crystal substrate, the device regions can be formed above the substrate to form stacked transistors, which provide greater density and lower cost. However, the polysilicon channels provide for smaller on-currents compared to monocrystalline silicon channels. The TFTs are most commonly used in flat panel displays as switching transistors and in Static Random Access Memories (SRAM) as load devices.
A structural invention known as double-gated polysilicon TFT has been found to provide increased on-current, twice as much as the on-current from a single gated device. Hashimoto et al., (in "Thin Film Effects of Double-Gate polysilicon MOSFET", Extended Abstracts of the 22nd conference on Solid State Devices and Materials, Sendal, 1990, ppp 393-396), describe a double gated TFT device, wherein the channel body polysilicon layer is sandwiched between a top and a bottom electrode. The top and bottom gate electrodes of the device described in Hashimoto et al, is shown in FIG. 1, and appear to be patterned using separate lithographic process steps. Hashimoto's study further showed that by using a thinner polysilicon channel in combination with the two gates, the on-current can be increased by one to two orders of magnitude. K. Itabashi et al. also describe the use of a double-gated PMOS thin film transistor load device in a 16 Mb SRAM, in their paper titled, "A Split Wordline Cell For 16 Mb SRAM Using Polysilicon Sidewall Contacts", IEDM pp 477-480, 1991. The Itabashi's SRAM cell was built using 5 polysilicon levels (figure not shown in here), the lowermost polysilicon is the gate electrode of the MOS transistor, polysilicon layers 2, 3 and 4 defined the dual gated TFT transistor and the topmost polysilicon layer is the ground plane. Itabashi's process involves the etching of contact openings through polysilicon layers 2 and 3 and the intervening insulators, such that when polysilicon layer 4 is deposited and patterned, it makes sidewall contact to electrodes 2 and 3 (in separate locations). Thus, the bottom and top gates of the TFT are connected together and the TFT channel layer and the MOS gate electrode are connected together. In both of these prior art methods, the process involves patterning bottom and top gates in separate steps which increase the process complexity.
Another desired feature in TFTs is drain off-sets, which are lightly doped body silicon parts outside of the gate electrode/channel region, somewhat similar to lightly doped drains (LDDs) in FETs. Liu et al. ("High Reliability, high Performance 0.35 um Gate Inverted TFT for 16 Mbit SRAM Applications Using Self-Aligned LDD Structures", 1992 IEDM 823-826) describe forming LDD type spacer regions in a bottom gate TFT using sacrificial sidewall spacers. Drain off-sets reduce punch-thru problems and off-state leakage current.
Mori (U.S. Pat. No. 5,160,491) teaches forming a field effect transistor on the sidewalls of a trench. In Mori's device, the source, channel and drain are vertically disposed adjacent to a trench and the gate insulator and electrode are formed on the sidewall of the trench. The vertically formed FET is claimed to provide higher density. Shimbo (U.S. Pat. No. 4,924,279) describes a thin film transistor device somewhat similar to Mori's in its structure. In Shimbo's process, a vertical step is formed by a sandwich of layers; a source layer, an insulating spacer and a drain layer. Along the sidewall of this sandwich, a channel, gate insulator and gate electrode are deposited sequentially. This structure has been claimed to provide a short channel length (the thickness of the insulator spacer) and further the channel region is shielded from light radiation which is especially of benefit in TFT display devices using liquid crystal devices. Whereas, Shimbo's process is interesting, it does not provide a bottom gate TFT. Further, the location of source and drain in the Shimbo device configuration would require additional process steps to connect them to other device parts.
Ishihara (U.S. Pat. No. 5,001,540) forms a gate stack and deposits a TFT device polysilicon layer going over the side of the gate stack. A sidewall insulator is used to protect the vertical part of the device layer, while the horizontal unprotected parts are implanted to define the source and drain extensions. The width of the sidewall spacer determines the off-set region length in the Ishihara's process. Further, Ishihara's method fails to teach a process for forming of a dual gated TFT. In Ishihara's device the off-set region is simply the extension of the channel layer with the same dopant concentration as the channel layer. There is no flexibility to adjust the off-set region dopant concentration to optimize the resistivity of the off-set regions. The resistance may be too high for applications requiring faster switching speed and larger "on" current.
Thus, there is a clear need in TFT manufacturing for a simplified and high yielding process for forming dual-gated TFTs, that is self -aligning, allows for the formation of off-set regions of selected resistivity and involves fewer, easily controllable manufacturing steps.